Effect of fin shape of tapered FinFETs on the device performance in 5-nm node CMOS technology

In this paper, we investigate the impact of fin-shape, dimension, and geometry of tapered FinFET with 5-nm node (N5) technology using TCAD simulation. Fixed gate length (L_G) of 9 nm, spacer length (L_SP) of 7 nm, and bottom fin-width (F_WB) of 6 nm were used. The other parameters, such as top fin-width (F_WT) and fin-height (F_H) were modulated to see the impact on the electrical characteristic and physical behaviors of the device. The simulation results show that increasing F_H can enhance the saturation current (I_SAT) effectively. However, the threshold voltage (V_TH) will suffer so much. In addition, a higher F_H means that a larger aspect ratio, thus it is not easy to fabricate in the manufacturing process. On the other hand, the saturation current can be improved by widening F_WB. Nevertheless, it may not be a good choice because a wider F_WB lets a larger cross-section device area for epitaxy source and drain. Tuning F_WT may be the best choice to have a current gain. Additional 1 nm F_WT can enhance approximately 30% of the saturation current. Moreover, the V_TH has no significant impact and it is good for source-drain epitaxy. By careful control of F_H and F_WT, the device performance can be predicted very well. As the results, Moore's law still can work even in N5 CMOS technology.