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FPGA的超声相控阵系统接收波形合成结构
引用本文:王华,单宝华,欧进萍.FPGA的超声相控阵系统接收波形合成结构[J].哈尔滨工业大学学报,2009,41(2):120-123.
作者姓名:王华  单宝华  欧进萍
作者单位:王华,WANG Hua(哈尔滨工业大学,交通科学与工程学院,哈尔滨,150090);单宝华,SHAN Bao-hua(哈尔滨工业大学,土木工程学院,哈尔滨,150090);欧进萍,OU Jin-ping(哈尔滨工业大学,土木工程学院,哈尔滨,150090;大连理工大学,大连,116024)  
基金项目:国家高技术研究发展资助项目,国家自然科学基金 
摘    要:为了解决在超声相控阵系统设计中,接收波形合成需要将各阵列阵元接收到的信号进行相干叠加的问题,提出了一种能够实现1 ns延迟分辨率的数字接收波形合成设计.该设计采用锁相环(PLL)的相移技术首先产生6个周期为6 ns、相位差为1 ns的时钟信号.根据焦点的不同,6个时钟信号被选择作为异步采样时钟.采样数据同步后进行叠加,得到数字超声合成波形.波形合成硬件除A/D转换器外都集成在FPGA芯片内部.FPGA芯片在接收波形中的应用使得编程灵活和体积减小,得到了非常低廉的设计.完成了该设计的仿真实验并给出了实验数据.实验结果表明:该设计能够稳定和精确的实现1 ns分辨率的接收波形合成.

关 键 词:超声相控阵  波形合成  FPGA  锁相环

A novel architecture of receive beamforming for ultrasonic phased array system based on FPGA
WANG Hua,SHAN Bao-hua,OU Jin-ping.A novel architecture of receive beamforming for ultrasonic phased array system based on FPGA[J].Journal of Harbin Institute of Technology,2009,41(2):120-123.
Authors:WANG Hua  SHAN Bao-hua  OU Jin-ping
Affiliation:2,3(1.School of Transportation Science and Technology,Harbin Institute of Technology,Harbin 150090,China;2.School of Civil Engineering,Harbin Institute of Technology,Harbin 150090,China;3.Dalian University of Technology,Dalian 116024 China)
Abstract:Aimed at the coherent addition of signals received by the array elements in the design of receive beamforming in ultrasonic phased array system,this paper presents a novel design of digital receive beamforming with 1ns delay resolution.The design adopts the phase shifting with PLL to generate six clock signals with period of 6ns and phase difference of 1ns.And the six clock signals are selected as asynchronous sampling clocks corresponding to different focal points.The digital beamformed ultrasonic wave is obtained after the sampled data are synchronized and added.The receive beamforming hardware is built with FPGA components except the A/D converters.The use of FPGA in the design of receive beamforming results in flexible programming and small volume.A particular simulation of the design is presented together with experimental performance figures.Results show that the proposed design can synthesize the receive beamforming of 1ns resolution with high stability and accuracy.
Keywords:FPGA
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