A novel simplified process for fabricating a very high densityp-channel trench gate power MOSFET |
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| Authors: | Kee Soo Nam Ju Wook Lee Sang-Gi Kim Tae Moon Roh Hoon Soo Park Jin Gun Koo Kyung Ik Cho |
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| Affiliation: | Microelectron. Technol. Lab., Electron. & Telecommun. Res. Inst., Taejon; |
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| Abstract: | A novel simplified fabrication method of a very high density p-channel trench gate power MOSFET using four mask layers and nitride/TEOS sidewall spacers is realized. The proposed process showed improved on-resistance characteristics of the device with increasing cell density and the cost-effective production capability due to the lesser number of processing steps. By using this process technique, a remarkably increased high density (100 Mcell/inch2) trench gate power MOSFET with a cell pitch of 2.5 μm could be effectively realized. The fabricated device had a low specific on-resistance of 1.1 mΩ-cm2 with a breakdown voltage of -36 V |
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