基于FPGA的Turbo码译码器的设计

介绍了一种基于现场可编程门阵列（FPGA）的Turbo码译码器的完整的设计方案和设计结果，采用Max-Log-MAP译码算法，用Verilog语言编程，提出了正序运算和逆序运算同时进行，以及采用数组型存储器存储中间运算结果的方案，使译码速度得到提高。文中给出了Turbo码译码原理、Max-Log-MAP算法分析、基于FPGA的设计方案及实现框图、算法时序图及速度分析、仿真波形图及性能分析，结果表明，该方案正确可行，译码/纠错正确无误，且译码速度快。

Design of the Turbo decoder with FPGA

The design proposal and result of a FPGA-based Turbo decoder is introduced. Using the Max-Log-MAP decoding algorithm and the Verilog language for programming, the positive sequence operation and the reverse order operation can be simultaneously carried, and the intermediate results can be stored in array-based memory，which has enabled the decoding speed to be improved. The Turbo decoding theory, the Max-Log-MAP algorithmic analysis, the block diagram based on FPGA design and implementation, algorithm timing diagram and velocity analysis, are also presented. Results indicates that the program is correct and feasible, decoding/error correction is unmistakable, and the decoding speed is quick.