一种系统化流水线控制方法

本文研究设计了一种系统化流水线控制方法及其递推理论公式。基于该方法,在0.18um CMOS工艺条件下,实现系统时钟为200MHz的兼容于ARMv4指令集微处理器,指令执行效率最低为150 MIPS。每一级流水线本质为本级流水线是否保存指令执行结果、本级流水线指令是否执行下一级流水线、是否自锁执行本级流水线。根据这一本质,只需单独考虑每一类指令的执行过程,而无需考虑指令之间的复杂关系,使系统设计简单化,其优点在于对流水线深度不敏感,控制结构类似,适合于高深度、最优深度流水线设计,解决流水线控制逻辑的设计难度,提高微处理器指令执行效率。

A Systematic Pipeline Control Method

This paper presents a systematic pipeline control method.With this method a 200MHz ARMv4 instruction set compatible Micro Processor,whose minimum instruction execution rate reaches 150MIPS,is implemented in Chartered 0.18um technology.The pipeline instinct lies on whether the instruction execution results of the current pipeline stage will be sampled,whether the instruction will be executed in the following pipeline stage or interlocked in the current pipeline stage.It is only necessary to care about the execution flow of any single instruction type,without considering the complicated relationship between instructions,which simplifies the pipeline control logic designing of the Micro Processor.The application of this pipeline control method is well suitable for Micro Processor with high pipeline depth because this method is pipeline depth insensitive,implemented with similar control architecture of each pipeline stage.