用于高速高精度流水线ADC的开关电容比较器

在65 nm CMOS工艺条件下,设计了一种用于高速高精度流水线ADC的开关电容比较器。采用单电容结构,实现了比较结果的最小化传输延迟。利用正反馈电容将采样网络的实极点调制为复极点,以减小采样传输延迟。用静态锁存器替代高速双尾动态锁存器,以适应正反馈的电容结构。数字驱动部分采用正反馈方式,以提升传输速度。Spectre仿真结果表明,在14位精度下,10 GHz带宽比较器的采样网络具有与20 GHz带宽MDAC的采样网络相同的传输延迟,从锁存器开始锁存到数字驱动输出的总传输延迟小于50 ps。

A Switched Capacitor Comparator for High Speed and High Resolution Pipeline ADC

A switched capacitor comparator for high speed and high resolution pipelined ADC was designed in a 65 nm CMOS process. A single capacitor structure had been used to minimize the transmission delay of the comparison results for the comparator. The real pole of the sampling network was modulated to a complex pole by using the positive feedback capacitance to reduce the sampling transmission delay. And the static latch was used instead of the high-speed double tailed dynamic latch, which had adapted to this positive feedback capacitor structure. Positive feedback mode had been adopted for the digital drive part to enhance the transmission speed. The Spectre simulation results showed that the sampling network of 10 GHz bandwidth comparator had the same transmission delay as that of the sampling network of 20 GHz bandwidth MDAC at 14-bit accuracy, and the total transmission delay from the beginning of latching to digital output driving was less than 50 ps.