| 基于总线功能模型的SoC仿真加速技术 |
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| 引用本文： | 杨军,付亮,张志敏.基于总线功能模型的SoC仿真加速技术[J].微电子学与计算机,2008,25(1):45-47,51. |
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| 作者姓名： | 杨军 付亮 张志敏 |
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| 作者单位： | 1. 中国科学院,计算技术研究所,北京,100080;中国科学院,研究生院,北京,100039
2. 中国科学院,计算技术研究所,北京,100080 |
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| 基金项目： | 国家“八六三”计划项目(2002AA1Z1040)，中科院计算所创新课题(20056170)，北京市工业促进局技术发展资金项目(京财经一指[2005]1858号) |
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| 摘 要： | SoC是IC设计的发展趋势,而随着SoC的日趋复杂,对系统仿真带来了越来越艰巨的挑战,基于EDA厂商提供的传统仿真环境已经不能充分满足SoC的开发需求,针对此问题提出了基于总线功能模型的仿真加速策略,测试结果表明,提出的技术策略可获得45%的仿真性能提升。
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| 关 键 词： | 仿真加速 SoC 验证 总线功能模型 CPU |
| 文章编号： | 1000-7180（2008）01-0045-03 |
| 收稿时间： | 2007-03-22 |
| 修稿时间： | 2007年3月22日 |
SoC Simulation Speed-up Technology Based on Bus Functional Model |
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| YANG Jun,FU Liang,ZHANG Zhi-min.SoC Simulation Speed-up Technology Based on Bus Functional Model[J].Microelectronics & Computer,2008,25(1):45-47,51. |
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| Authors: | YANG Jun FU Liang ZHANG Zhi-min |
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| Abstract: | SoC is becoming the trend of IC design. With the ever-increasing complexity of SoC, there are more and more arduous challenges facing system simulation process during SoC development. And the traditional simulation platform provided by EDA vendors can not satisfy SoC designers' need. In this paper, a simulation speed-up strategy is presented to solve this problem with the experimental results which show that this strategy can accelerate the simulation speed in 45 percent. |
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| Keywords: | simulation speed-up SoC verification bus functional model CPU |
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