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SRAM版图布局方向对产品失效率的影响
引用本文:梁家鹏,唐晓柯,关媛,李大猛,李秀全,王小曼.SRAM版图布局方向对产品失效率的影响[J].半导体技术,2021,46(3):236-240.
作者姓名:梁家鹏  唐晓柯  关媛  李大猛  李秀全  王小曼
作者单位:北京智芯微电子科技有限公司国家电网公司重点实验室电力芯片设计分析实验室,北京 100192;北京智芯微电子科技有限公司北京市电力高可靠性集成电路设计工程技术研究中心,北京 100192
摘    要:静态随机存储器(SRAM)是集成电路中重要的存储结构单元。由于其制备工艺复杂、关键尺寸较小、对设计规则的要求最为严格,因此SRAM的质量是影响芯片良率的关键因素。针对一款微控制单元(MCU)芯片的SRAM失效问题,进行逻辑地址分析确认失效位点,通过离子聚焦束(FIB)切片及扫描电子显微镜(SEM)分析造成失效的异常物理结构,结合平台同类产品的设计布局对比及生产过程中光刻工艺制程的特点,确认失效的具体原因。对可能造成失效的工艺步骤或参数设计实验验证方案,根据验证结果制定相应的改善措施,通过良率测试及SEM照片确认改善结果,优化工艺窗口。当SRAM中多晶硅线布局方向与测试单元中一致时,工艺窗口最大,良率稳定;因此在芯片设计规则中明确SRAM结构布局方向,对于保证产品的良率具有重要意义。

关 键 词:静态随机存储器(SRAM)  版图布局  光刻  关键尺寸  工艺窗口

Influence of the Layout Direction of the SRAM on Product Failure Rate
Liang Jiapeng,Tang Xiaoke,Guan Yuan,Li Dameng,Li Xiuquan,Wang Xiaoman.Influence of the Layout Direction of the SRAM on Product Failure Rate[J].Semiconductor Technology,2021,46(3):236-240.
Authors:Liang Jiapeng  Tang Xiaoke  Guan Yuan  Li Dameng  Li Xiuquan  Wang Xiaoman
Affiliation:(State Grid Key Laboratory of Power Industrial Chip Design and Analysis Technology,Beijing Smart-Chip Microelectronics Technology Co.,Ltd.,Beijing 100192,China;Beijing Engineering Research Center of High-Reliability IC with Power Industrial Grade,Beijing Smart-Chip Microelectronics Technology Co.,Ltd.,Beijing 100192,China)
Abstract:The static random access memory(SRAM)is an important storage unit in integrated circuits.Because of its complex preparation process,small critical dimension and strict design rules,the quality of SRAM is the key factor affecting the yield of chip.In order to solve the problem of SRAM failure of a micro control unit(MCU),logical address analysis was carried out to confirm the failure site.The abnormal physical structure caused by the failure was analyzed by focused ion beam(FIB)slice and scanning electron miroscopy(SEM).Combined with the design layout comparison of similar products of the platform and the characteristics of lithography process in the production process,the specific cause of the failure was confirmed.For the process steps or parameters that may cause failure,the experimental verification scheme was designed,and the corresponding improvement plan was made according to the verification results.The improvement results are confirmed by the yield test and SEM images,and the process window is optimized.When the layout direction of polysilicon lines in SRAM is consistent with that in the test cell,the process window is the largest and the yield is stable.Therefore,it is important to specify the layout direction of the SRAM structure in chip design rules to ensure the yield of products.
Keywords:static random access memory(SRAM)  layout  lithography  critical dimension  process window
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