晶圆级多层堆叠技术

随着5G和人工智能等新型基础设施建设的不断推进,单纯通过缩小工艺尺寸、增加单芯片面积等方式带来的系统功能和性能提升已难以适应未来发展的需求。晶圆级多层堆叠技术作为能够突破单层芯片限制的先进集成技术成为实现系统性能、带宽和功耗等方面指标提升的重要备选方案之一。对目前已有的晶圆级多层堆叠技术及其封装过程进行了详细介绍;并对封装过程中的两项关键工艺,硅通孔工艺和晶圆键合与解键合工艺进行了分析;结合实际封装工艺对晶圆级多层堆叠过程中的可靠性管理进行了论述。在集成电路由二维展开至三维的发展过程中,晶圆级多层堆叠技术将起到至关重要的作用。

Wafer-Level Multilayer Stacking Technology

With the continuous promotion of new infrastructures such as 5 G,artificial intelligence,etc,it is difficult to meet the future demands for the development by simply improving system func-tionality and performance through process dimension reduction,single-chip area increase,etc.Wafer-level multilayer stacking technology,as an advanced integration technology which can break through the limitations of single layer chip,has become one of the most important options to achieve the improvements of system performance,bandwidth and power consumption.The currently available wafer-level multilayer stacking technologies and their packaging processes are described in detail.Two key processes in the packaging,such as through-silicon via process and wafer bonding and de-bonding process are analyzed.Then the reliability management in wafer-level multilayer stacking is discussed in the context of the actual packaging process.The wafer-level multilayer stacking technology will play a crucial role in the development of integrated circuits from two-dimension to three-dimension.