Monitoring machine based synthesis technique for concurrent error detection in finite state machines |
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Authors: | R A Parekhji G Venkatesh S D Sherlekar |
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Affiliation: | (1) Department of Computer Science and Engineering, Indian Institute of Technology, 400076 Bombay, India |
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Abstract: | This paper discusses a new design methodology for concurrent error detection in synchronous sequential circuits based on the
use of monitoring machines. In this approach, an auxiliary sequential circuit, called the monitoring machine, operates in
lock-step with the main machine, such that any fault in either of the two machines is immediately detected. This methodology
is independent of the fault model. It can be applied to FSMs with pre-encoded states and can also be used for ones being synthesised.
It also provides a systematic framework for the combined optimisation of the main and monitoring machines, and for exploring
tradeoffs in their implementation.
The design of monitored sequential circuits is a two-fold problem; namely one of designing an optimal monitoring machine given
the main machine, and the other of encoding the main machine states so that the resulting monitoring machine is minimal. This
paper formally discusses the design of both the main and monitoring machines and techniques for their combined optimisation.
Tradeoffs in their implementation based on selective fault detection are also examined.
Through experimental results, it is shown that the proposed synthesis technique is eminently suitable for the design of low-cost
sequential circuits with concurrent error detection. The monitoring machine is less costly than the main machine. It is also
not identical to it. As a result, a monitored sequential circuit has significantly lower hardware cost and improved fault
coverage than previous implementations.
Presently at Texas Instruments (India) Ltd., Bangalore, India. |
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Keywords: | concurrent error detection monitoring machines finite state machine synthesis |
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