| 基于FPGA高速并行采样技术的研究 |
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| 引用本文： | 洪萌,耿相铭.基于FPGA高速并行采样技术的研究[J].现代电子技术,2011,34(5):180-182. |
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| 作者姓名： | 洪萌 耿相铭 |
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| 作者单位： | 上海交通大学电子工程系,上海,200240 |
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| 摘 要： | 介绍一种基于四通道ADC的高速交错采样设计方法以及在FPGA平台上的实现。着重阐述四通道高速采样时钟的设计与实现、高速数据的同步接收以及采样数据的校正算法。实验及仿真结果表明,同步数据采集的结构设计和预处理算法,能良好抑制并行ADC输出信号因相位偏移、时钟抖动等造成的失配误差。
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| 关 键 词： | 交错采样 高速采样时钟 同步接收 信号处理 |
Research of High-speed Parallel Sampling Technology Based on FPGA |
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| HONG Meng,GENG Xiang-ming.Research of High-speed Parallel Sampling Technology Based on FPGA[J].Modern Electronic Technique,2011,34(5):180-182. |
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| Authors: | HONG Meng GENG Xiang-ming |
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| Affiliation: | HONG Meng,GENG Xiang-ming(Shanghai Jiaotong University,Shanghai 200240,China) |
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| Abstract: | The design method of a high-speed interleaved sampling system based on four-channel analog-to-digital converter(ADC) and its realization on Virtex-5 FPGA platform of Xilinx are introduced.The design of four-channel high-speed sampling clock,the synchronus receiving method of high-speed data and correction algorithm of sampling data are emphasized.Simulation results indicate that the structural design of the synchronus data sampling system and the pre-processing algorithm can suppress the mismatch error of p... |
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| Keywords: | time-interleaved sampling high-speed sampling clock synchronous reception signal processing |
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