面向低电压供电数字电路的容错计算系统结构设计

为实现低功耗设计,数字电路的工作电压被不断降低,使得电路计算呈现概率特性.针对电路概率特性的实际应用,提出了将缩短精度冗余(RPR)算法与三模冗余(TMR)算法和冗余余数系统(RRNS)纠错算法结合的错误容忍的DSP系统设计方法,即RPR-TMR结构和RPR-RRNS结构;比较分析了PR-TMR和RPR-RRNS结构的综合性能,在低电压供电条件下该结构可以改善电路的性能,从而为概率器件在DSP中的应用提供了一种可行的设计思路.

Fault-Tolerance Computing Architecture Design for Low Suppling Voltage

In order to achieve low power consumption, the supply voltage is reduced gradually but this increases the probabilistic characteristic of digital circuits. In this paper, we propose the design method which combines of the reduced precision redundancy (RPR) algorithm with triple-modular redundancy (TMR) algorithm and Redundant residue number systems (RRNS) algorithm, referred as RPR-TMR and RPR-RRNS architectures respectively. The performance of these two kinds of structures is designed and analyzed. The results of case study show that the proposed of architectures can archive low power consumption and high output SNR.