Fully depleted silicon on insulator MOSFETs on (1 1 0) surface for hybrid orientation technologies

Effective memory performance of the nonvolatile memory/thin film transistor (NVM/TFT) devices needs good TFT characteristics. The reduction in leakage current of the TFT devices was accomplished with the gate offset (GOF) structure. A simplified fabrication process for the GOF NVM is introduced in this study using the insulator over-etching approach. Nonvolatile memory devices on glass using SiO₂/SiO_x/SiO_xN_y stack with an offset length of 0, 0.2, 0.4, and 0.6 μm were investigated. The highly selective etching process and the short offset length help to avoid the problem of the gate aluminum collapsing on the source/drain electrodes. The TFT characteristics of the GOF structures displayed the remarkable improvement in leakage from 1.1 × 10^?11 A, for the TFT without an offset region, to the low OFF current of 1.34 × 10^?12 A for the device with a 0.6 μm offset length. The longer offset length gave the lowest OFF current. The degradation in transconductance and the threshold voltage was negligible with the g_m values of about 3 × 10^?6 S and ΔV_th of about 0.2 V, respectively. The switching characteristics remained similar for all the devices. Additionally, the GOF structures slightly enhanced the retention characteristics. The memory window of the NVM without the offset after a retention time of 10,000 s was 58%, lower than the over 69% of the GOF devices. Therefore, the application of the GOF structure to reduce the leakage of the NVM/TFT proved to be effective.