基于忆阻器的乘法器电路设计

忆阻器作为一种非易失性的新型电路元件，在数字逻辑电路中具有良好的应用前景。目前，基于忆阻器的逻辑电路主要涉及全加器、乘法器以及异或(XOR)和同或(XNOR)门等研究，其中对于忆阻乘法器的研究仍比较少。该文采用两种不同方式来设计基于忆阻器的2位二进制乘法器电路。一种是利用改进的“异或”及“与”多功能逻辑模块，设计了一个2位二进制乘法器电路，另一种是结合新型的比例逻辑，即由一个忆阻器和一个NMOS管构成的单元门电路设计了一个2位二进制乘法器。对于所设计的两种乘法器进行了比较，并通过LTSPICS仿真进行验证。该文所设计的乘法器仅使用了2个N型金属-氧化物-半导体(NMOS)以及18个忆阻器(另一种为6个NMOS和28个忆阻器)，相比于过去的忆阻乘法器，减少了大量晶体管的使用。

Design of Memristor Based Multiplier Circuits

As a new non-volatile electronic device, memristor has a good application prospect in digital logic circuits. At present, memristor based logic circuits mainly involve the research of full adder, multiplier, exclusive-OR (XOR) and equivalence (XNOR), etc., among which there is little research on memristor based multiplier. The 2-bit binary multiplier circuit is designed in two different ways based on memristor. One is to design a 2-bit binary multiplier circuit by using the improved XOR and AND multifunctional logic modules. The other is to design a 2-bit binary multiplier by combining a new type of ratio logic, i.e. a unit gate circuit consisting of one memristor and one NMOS transistor. The two multipliers are compared and validated by LTSPICS simulation. The multiplier designed in this paper only uses 2 N-Metal-Oxide-Semiconductor (NMOS) and 18 memristors (the other is 6 NMOS and 28 memristors). Compared with previous memristor based multipliers, the multipliers in this paper reduce the number of transistors.