Single error correcting and double error detecting coding scheme |
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| Authors: | Lala PK Thenappan P Anwar MT |
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| Affiliation: | Dept. of Comput. Sci. & Comput. Eng., Univ. of Arkansas, Fayetteville, AR, USA; |
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| Abstract: | A new coding technique for single error correction and double error detection in computer memory systems is proposed. The number of 1s in the parity check matrix for the proposed coding is fewer than all currently available codes for this purpose, except in two cases when they are almost equal to that obtained by Hsiao code. This results in simplified encoding and decoding circuitry for error detection and correction. |
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