| 数字扫频仪中衰减电路的设计 |
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| 引用本文： | 马知远,范越,邓彬伟.数字扫频仪中衰减电路的设计[J].山西电子技术,2011(2):16-17,20. |
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| 作者姓名： | 马知远 范越 邓彬伟 |
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| 作者单位： | [1]海军工程大学电子工程学院,湖北武汉430033 [2]黄石理工学院电气与电子信息工程学院,湖北黄石435003 |
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| 摘 要： | 衰减电路是扫频仪中的重要组成部分,它的性能与精度直接影响整个仪器的测量精度。针对目前国内的扫频仪衰减精度不高和衰减步进值过大等问题,分析了基于AD834模拟乘法器和DDS芯片中的数字乘法器实现0.1 dB步进衰减的两种设计方案,提出了扫频仪中衰减器的设计方法,提高了扫频仪的测量范围和精度。
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| 关 键 词： | 衰减电路 扫频仪 乘法器 |
Design of Attenuator in the Digital Frequency Sweep Tester |
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| Ma Zhi-yuan,Fan Yue,Deng Bin-wei.Design of Attenuator in the Digital Frequency Sweep Tester[J].Shanxi Electronic Technology,2011(2):16-17,20. |
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| Authors: | Ma Zhi-yuan Fan Yue Deng Bin-wei |
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| Affiliation: | 1.Electronic Engineering College,Naval University of Engineering,Wuhan Hubei 430033,China;2.School of Electronic and Information Engineering,Huangshi Institute of technology,Huangshi Hubei 435003,China) |
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| Abstract: | Attenuator is a very important part in frequency sweep tester.It can affect the test accuracy of the tester.To solve the problems in domestic frequency sweep tester such as low accuracy and large attenuation step,this paper analyzes two method of 0.1 dB attenuator step which based on analog multiplier AD834 and digital multiplier in the DDS chip.The new method extends the test range and improves the test accuracy. |
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| Keywords: | attenuator frequency sweep tester multiplier |
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