A 80-MHz bandpass ΔΣ modulator for a 100-MHz IFreceiver

A fully differential fourth-order bandpass ΔΣ modulator is presented. The circuit is targeted for a 100-MHz GSM/WCDMA-multimode IF-receiver and operates at a sampling frequency of 80 MHz. It combines frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an intermediate frequency of 100 MHz to a digital intermediate frequency of 20 MHz. The modulator is based on a double-delay single-op amp switched-capacitor (SC) resonator structure which is well suited for low supply voltages. Furthermore, the center frequency of the topology is insensitive to different component nonidealities. The measured peak signal-to-noise ratio is 80 and 42 dB for 270 kHz (GSM) and 3.84-MHz (WCDMA) bandwidths, respectively. The circuit is implemented with a 0.35-μm CMOS technology and consumes 56 mW from a 3.0-V supply