| 时钟树性能的研究及改进方法 |
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| 引用本文： | 柯烈金,吴秀龙,徐太龙.时钟树性能的研究及改进方法[J].数字社区&智能家居,2011(16). |
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| 作者姓名： | 柯烈金 吴秀龙 徐太龙 |
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| 作者单位： | 安徽大学电子信息工程学院; |
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| 基金项目： | 安徽省教育厅重点项目(KJ2010A022) |
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| 摘 要： | 分析了时钟树的性能要素:时钟树长度、时钟树偏差和时钟信号占空比,分析了改进时钟树性能的多个策略:合理的floorplan、合理的时钟创建源点、避免宏模块时钟端对时钟树平衡的不利影响、正确处理分离时钟门控、使用clock inverter改善时钟信号占空比。
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| 关 键 词： | 时钟树 时钟树长度 时钟树平衡 占空比 |
Research and Methodologies of Improving Quality of Clock Tree |
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| KE Lie-jin,WU Xiu-long,XU Tai-long.Research and Methodologies of Improving Quality of Clock Tree[J].Digital Community & Smart Home,2011(16). |
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| Authors: | KE Lie-jin WU Xiu-long XU Tai-long |
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| Affiliation: | KE Lie-jin,WU Xiu-long,XU Tai-long(School of Electronics and Information Engineering,Anhui University,Hefei 230601,China) |
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| Abstract: | The elements of clock tree performance: clock tree insertion delay,clock skew and clock signal duty cycle are analyzed.The strategy of improving quality of clock tree are analyzed,the strategy includes reasonable floorplan,reasonable clock source,to avoid macro clock pin bring adverse to clock tree balance,handling the discrete clock gating correctly,improving clock signal duty cycle based on clock inverter. |
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| Keywords: | clock tree clock tree insertion delay clock tree balance duty cycle |
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