采用新的抬高源漏工艺技术制作的全耗尽SOI CMOS器件和电路

采用新的工艺技术,成功研制了具有抬高源漏结构的薄膜全耗尽SOI CMOS器件.详细阐述了其中的关键工艺技术.器件具有接近理想的亚阈值特性,nMOSFETs和pMOSFETs的亚阈值斜率分别为65和69mV/dec.采用抬高源漏结构的1.2μm nMOSFETs的饱和电流提高了32%,pMOSFETs的饱和电流提高了24%.在3V工作电压下101级环形振荡器电路的单级门延迟为75ps.

Elevated Source/Drain Engineering by Novel Technology for Fully-Depleted SOI CMOS Devices and Circuits

0. 35μm thin-film fully-depleted SOI CMOS devices with elevated source/drain structure are fabricated by a novel technology. Key process technologies are demonstrated. The devices have quasi-ideal subthreshold properties; the subthreshold slope of nMOSFETs is 65mV/decade,while that of pMOSFETs is 69mV/decade. The saturation current of 1.2μm nMOSFETs is increased by 32 % with elevated source/drain structure,and that of 1.2μm pMOSFETs is increased by 24%. The per-stage propagation delay of 101-stage fully-depleted SOI CMOS ring oscillator is 75ps with 3V supply voltage.