一种具有自校准功能的CMOS分数数字锁相环

提出了一种数字锁相环(DPLL),它的相频检测器采用全新的设计方法和自校准技术,具有工作频率范围宽,抖动低,快速锁定的优点.锁相环在1.8V外加电源电压时,工作在60～600MHz的频率范围内.采用分数分频技术,加速锁定过程并具有较小的输出频率间隔,利用∑-Δ调制改善相位噪声性能.设计在SMIC 0.18μm,1.8V,1P6M标准CMOS工艺上实现,峰-峰相位抖动小于输出信号周期的0.8%,锁相环的锁定时间小于参考频率预分频后信号周期的150倍.

A Fractional-N CMOS DPLL with Self-Calibration

A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range, low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fractional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time, a high frequency resolution, and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0.8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.