Hybrid dual gate ferroelectric memory for multilevel information storage |
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| Affiliation: | 1. Department of Electrical Engineering, Graduate School of Science and Technology, Meiji University, 1-1-1 Higashimita, Tama-ku, Kawasaki, Kanagawa 214-8571, Japan;2. International Center for Materials Nanoarchitectonics (WPI-MANA), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044, Japan;3. Research Fellow of Japan Society for the Promotion of Science (JSPS), 5-3-1 Kojimachi, Chiyoda-ku, Tokyo 102-0083, Japan |
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| Abstract: | Here, we report hybrid organic/inorganic ferroelectric memory with multilevel information storage using transparent p-type SnO semiconductor and ferroelectric P(VDF-TrFE) polymer. The dual gate devices include a top ferroelectric field-effect transistor (FeFET) and a bottom thin-film transistor (TFT). The devices are all fabricated at low temperatures (～200 °C), and demonstrate excellent performance with high hole mobility of 2.7 cm2 V?1 s?1, large memory window of ～18 V, and a low sub-threshold swing ～?4 V dec?1. The channel conductance of the bottom-TFT and the top-FeFET can be controlled independently by the bottom and top gates, respectively. The results demonstrate multilevel nonvolatile information storage using ferroelectric memory devices with good retention characteristics. |
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| Keywords: | Ferroelectric Memory Dual gate Tin monoxide p-type semiconductor |
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