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Controlled growth of a graphene charge-floating gate for organic non-volatile memory transistors
Affiliation:1. Department of Electrical Engineering and Computer Science, Inter University Semiconductor Research Center (ISRC), Seoul National University, Seoul 151–744, Republic of Korea;2. Department of Chemistry, Seoul National University, Seoul 151–747, Republic of Korea;1. Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center, Seoul National University, 1 Gwanak-ro, Gwanak-gu, Seoul 08826, Korea;2. Construction Equipment Technology Center, Korea Institute of Industrial Technology (KITECH), 13-13 Hayang-ro, Gyeongsan 38430, Korea;3. School of Electrical and Computer Engineering, University of Seoul, 163 Seoulsiripdaero, Dongdaemun-gu, Seoul 02504, Korea;1. Graduate Institute of Photonics and Optoelectronics, Department of Electrical Engineering, National Taiwan University, Taipei 10617, Taiwan;2. Institute of Electronics Engineering, National Tsing Hua University, Hsinchu 30010, Taiwan;3. Department of Photonics, National Chiao Tung University, Hsinchu 30010, Taiwan;4. Institute of Physics, National Chiao Tung University, Hsinchu 30010, Taiwan;1. Japan Advanced Institute of Science and Technology, 1-1 Asahidai, Nomi, Ishikawa, 923-1292, Japan;2. Faculty of Electrical-Electronic Engineering, University of Transport and Communications, No.3 Cau Giay Street, Dong Da, Hanoi, Viet Nam;3. Department of Material and Life Science, Osaka University, Suita, Osaka, 565-0871, Japan;4. Department of Chemistry and Nano Science, Ewha Womans University, Seoul, 120-750, Republic of Korea;5. Faculty of Science and Technology, Meijo University, SENTAN, Japan Science and Technology (JST), Nagoya, Aichi, 468-8502, Japan;6. Division of Innovative Research for Drug Design, Institute of Academic Initiatives, Osaka University, Suita, Osaka, 565-0871, Japan;1. State Key Laboratory of ASIC and System, Department of Microelectronics, SIST, Fudan University, Shanghai 200433, China;2. School of Physics and Astronomy, Queen Mary University of London, Mile End Road, London E1 4NS, United Kingdom;3. Royal Inst Technol KTH, iPack VINN Excellence Ctr, S-16440 Stockholm, Sweden
Abstract:We report memory application for graphene as a floating gate in organic thin-film transistor (OTFT) structure. For graphene floating gate, we demonstrate a simpler synthesis method to form a discrete graphene layer by controlling the growth time during a conventional CVD process. The resulting organic memory transistor with the discrete graphene charge-storage layer is evaluated. The device was demonstrated based on solution-processed tunneling dielectric layers and evaporated pentacene organic semiconductor. The resulting devices exhibited programmable memory characteristics, including threshold voltage shifts (∼28 V) in the programmed/erased states when an appropriate gate voltage was applied. They also showed an estimated long data retention ability and program/erase cycles endurance more than 100 times with reliable non-volatile memory properties although operated without encapsulation and in an ambient condition.
Keywords:Graphene  Pentacene  Non-volatile memory  Organic thin film transistor
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