An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET |
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Authors: | Pujarini Ghosh Subhasis Haldar R.S Gupta Mridula Gupta |
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Affiliation: | 1. Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, Benito Juarez Road, New Delhi 110021, India;2. Department of Physics, Motilal Nehru College, University of Delhi, New Delhi 110021, India;3. Department of Electronic & Communication Engineering, Maharaja Agrasen Institute of Technology, Sector-22, Rohini, Delhi 110085, India |
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Abstract: | In this paper, a drain current model incorporating drain-induced barrier lowering (DIBL) has been developed for Dual Material gate Cylindrical/Surrounding gate MOSFET (DMG CGT/SGT MOSFET) and the expressions for transconductance and drain conductance have been obtained. It is shown that DMG design leads to drain current enhancement and reduced output conductance. The effectiveness of DMG design was scrutinized by comparing with single metal gate (SMG) CGT/SGT MOSFET. Moreover, the effect of technology parameters variations workfunction difference has also been presented in terms of gate bias, drain bias, transconductance and drain conductance. Results reveal that the DMG SGT/CGT devices offer superior characteristics as compared to single material gate CGT/SGT devices. A good agreement between modeled and simulated results has also been obtained thus providing the validity of proposed model. |
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