LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier 期刊界 All Journals 搜尽天下杂志传播学术成果专业期刊搜索期刊信息化学术搜索

LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier

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收稿时间：	27 May 2011
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