A novel method to improve cell endurance window in source-side injection split gate flash memory |
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Authors: | Yong-Shiuan Tsair Yean-Kuen Fang Feng-Renn Juang Yu-Hsiung Wang Wen-Ting Chu Yung-Tao Lin Luan Tran |
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Affiliation: | 1. VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan;2. Taiwan Semiconductor Manufacturing Company, Hsinchu Science Park, Hsin-Chu 300, Taiwan |
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Abstract: | To enhance cell endurance window of a split gate flash memory, we used a ramp pulse with long rising time to replace the conventional square pulse for programming. The change is based on the study of the electric field at electron injection point (EG) related to programming time. Statistic measurements on various samples including different technologies, cell locations (even or odd) and rise times were done. The results confirm that the read currents shift under erase state (ΔIr1) could be improved significantly with an acceptable programming speed by the proposed method.For example, as increasing the rising time from 0.1 μs to 20 μs for the conventional square pulse and the ramp pulse respectively, after 1 M cycling the ΔIr1 is reduced from 64.8% to 36.2% with an acceptable minimum programming time of 12.5 μs. |
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