Chip warpage model for reliability prediction of delamination failures |
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Authors: | Se Young Yang Woon-Seong Kwon Soon-Bok Lee |
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Affiliation: | 1. Department of Mechanical Engineering, Massachusetts Institute of Technology, 77 Massachusetts Avenue, Cambridge, MA 02139, USA;2. Institute of Microelectronics, 11 Science Park Road, Singapore Science Park II, Singapore 117685, Singapore;3. Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology, 335 Gwahak-ro, Yuseong-gu, Daejeon 305-701, Republic of Korea |
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Abstract: | A new experimental method to predict reliability for ACA type packages under temperature cycling is developed and proposed. The method introduces a new damage parameter that can be easily measured by experiment. It is proved that the linear elastic parameter, dw/dT which represents the rate of change of chip warpage with respect to temperature, efficiently reflects the common failure mechanism of ACA type packages, the interfacial delamination between the chip and the adhesive. It is demonstrated, both experimentally and numerically, that the size of delamination affects the warpage behavior of the chip. The dw/dT of the chip is monitored in real time using laser interferometers under thermal fatigue cycles up to 3000. The gradual decrease in warpage due to progressive increase in delamination is clearly emerged. As a result, a reliability curve that can predict the size of delamination and remained life is obtained. The new long-term reliability prediction method developed in this study can be applied to various advanced packages, e.g. underfilled flip–chip or TSV stacked chip packages, that embrace interfacial delamination as primary failure mode. |
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