一种单锁存器CMOS三值D型边沿触发器设计

提出了一种只使用单个锁存器的CMOS三值D型边沿触发器设计.该电路是通过时钟信号的上升沿后产生的窄脉冲使锁存器瞬时导通完成取样求值.所提出的电路较之以往设计具有更为简单的结构,三值双轨输出时仅需24个MOS管.计算机模拟结果验证了所提出的触发器具有正确的逻辑功能、良好的瞬态特性和更低的功耗.此外,该设计结构极易推广至基值更高的多值边沿触发器的设计.

CMOS Ternary D-Type Edge-triggered Flip-Flop Using One Latch

A novel CMOS ternary D type edge triggered flip flop using a single latch is presented.In the proposed circuit,data are sampled into the latch during a short transparency period for rising edge of the clock signal.The proposed circuit has a simpler construction with respect to previously reported ternary flip flop.This simple flip flop with dual rail outputs uses only twenty four MOS transistors in addition to the clock driver,and hence requires a small silicon area.The computer simulation with PSPICE has validated that this flip flop can realize the expected logic function,has desirable transient characteristics and lower power dissipation.Furthermore,the proposed construction can be easily extended to the design of multiple valued edge triggered flip flop with a higher radix.