一种RTL级数据通路ODC低功耗优化算法

 本文提出了一种具有高计算效率和低硬件开销的门控时钟低功耗优化算法. 该算法在RTL级搜索数据通路的不可观察性（Observability Don′t Care）. 采用RTL级逻辑信号总线ODC模型和基于路径ODC的有向图遍历模型，减少了ODC计算负荷，提升了计算效率，使ODC适用于超大规模集成电路的低功耗优化. 引入数据通路ODC条件概率作为门控信号产生的重要依据，对ODC条件概率高的通路优先插入门控逻辑，可以极低硬件开销实现高效门控时钟网络. 实验结果显示，本算法与传统ODC算法相比计算负荷平均降低8倍，功耗平均下降12.35%，面积开销平均减少13.44%.

A RTL Level ODC Algorithm for Data Path Low Power Optimization

This paper proposes an efficient and low-overhead optimization algorithm for clock gating based low power design. It searches the Observability Don′t Care (ODC) conditions of data path at RTL level. It analyzes the ODC conditions of RTL logic level signal which is defined as Bus-ODC model. Data path is cut down into several short paths and computed ODC condition separately, which is defined as Path-ODC model. These two models can reduce the ODC computation load and improve the computation efficiency, and make it sufficient for VLSI low power optimization. Probability of ODC conditions is also proposed in this paper and used as an important basis of clock gating logic synthesis. It is preferred to insert clock gating logic into the data path with high probability of ODC condition. Probability driven clock gating logic synthesis improves the efficiency of clock gating network with tiny hardware overhead. Compared with the result of traditional ODC algorithm, computation load of RTL level ODC algorithm is only one-eight of that, power can be reduced by 12.35% and hardware overhead is cut down by 13.44% in average.