| 基于部分积优化的高速并行乘法器实现 |
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| 引用本文： | 李康,林钰凯,马佩军,史江义,梁亮.基于部分积优化的高速并行乘法器实现[J].微电子学与计算机,2011,28(1):61-63,68. |
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| 作者姓名： | 李康 林钰凯 马佩军 史江义 梁亮 |
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| 作者单位： | 西安电子科技大学宽禁半导体材料与器件国防重点实验室,陕西西安,71007 |
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| 摘 要： | 提出了部分积产生与压缩单元的改进结构,通过对部分积产生算法进行优化,采用选择器结构来替换传统的与或门,提高了部分积电路的性能,并降低了该模块的面积与功耗.对压缩单元的优化提高了部分积压缩的速度.对16×16并行乘法器综合验证表明,改进的乘法器性能提高14.5%,面积减少7.1%,同时功耗下降17.2%.
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| 关 键 词： | 数字信号处理 乘法器电路 编码 低功耗 |
Implementation of High-speed Parallel Multiplier Based on Optimized Partial Product |
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| LI Kang,LIN Yu-kai,MA Pei-jun,SHI Jiang-yi,LIANG Liang.Implementation of High-speed Parallel Multiplier Based on Optimized Partial Product[J].Microelectronics & Computer,2011,28(1):61-63,68. |
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| Authors: | LI Kang LIN Yu-kai MA Pei-jun SHI Jiang-yi LIANG Liang |
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| Affiliation: | LI Kang,LIN Yu-kai,MA Pei-jun,SHI Jiang-yi,LIANG Liang(Key Laboratory-wide Bandgap Semiconductor Materials and Device,Xidian University,Xi'an 710071,China) |
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| Abstract: | An improved architecture of partial product generation and compressing units is researched in this paper.By optimizing the partial product generating algorithm with multiplexers in stead of traditional AND and OR gates,the performance of partial product circuits is improved.Meanwhile,the area and power consumption of the module is also decreased.Optimized compressor units enhance the speed of partial product compression processing.The results of synthesis and verification for 16×16 parallel multiplier show that its performance was increased by 14.5%,as well as the area decreased by 7.1% and the power consumption reduced by 17.2%. |
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| Keywords: | digital signal processing multiplying circuits encoding low-power electronics |
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