一种用于数字PFC的嵌入式SARADC

设计了一个用于数字PFC(功率因数校正)的12位精度的逐次逼近(SAR)A/D转换器.对DAC模块中出现的电容寄生问题进行了详细分析,针对性提出了一种1-6-5式的新型电容分段结构,并采用伪差分结构消除电荷注入和时钟馈通引入的一阶效应,使ADC性能有很大提高.上述设计在0.35μm CMOS工艺下完成,目前该芯片正在流片中.仿真结果表明,在采样频率为0.98MSPS,输入信号为50kHz时,新型分段结构ADC的信噪比SNR与无杂散动态范围SFDR较六六分段约有6%的提高.

A Design of Embedded SAR ADC for Digital PFC

This paper presents a 12 bit SARADC for a system of digital Power Factor Correction.The questions about parasitic capacitor of DAC module have been analyzed and solved using a new architecture which is 1-6-5 capacitor segments.A pseudo-differential method is used to eliminate charge injection and degrade clock feed-through in order to improve the ADC.This design has been tape out using 0.35 μm CMOS process.Simulation results show that the SNR and the SFDR of this design are about 6% higher than those of 6-6 segment with a 50 kHz sinusoidal input under a 0.98 MHz sampling rate.