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| 常系数乘法器的VLSI高效设计 | |
| 引用本文： | 熊承义,高志荣,田金文.常系数乘法器的VLSI高效设计[J].军民两用技术与产品,2003(9):37-38,42. |
| 作者姓名： | 熊承义 高志荣 田金文 |
| 作者单位： | 1. 华中科技大学图像所,武汉,430074中南民族大学电子与信息工程学院,武汉,430074 2. 武汉科技学院计算机系,武汉,430074 3. 华中科技大学图像所,武汉,430074 |
| 摘 要： | 符号数的正则表示(CSD)是一种用最少的非零比特位来表示符号数的编码技术。介绍了一种基于二进制补码数实现CSD编码的转换算法。通过采用多种优化技术，提出了基于CSD编码技术的常系数乘法器的VLSI高效设计。采用Venlog硬件描述语言实现了一组小波滤波器的乘法单元的RTL描述。在Xilinx ISE4．1环境下对设计进行了功能仿真、综合和FPGA原型实现。 |
| 关 键 词： | 高速乘法器 正则符号数 VLSI 设计 硬件描述语言 数字信号处理 编码 |
| 文章编号： | 1009-8119(2003)09-0037-02 |
High Efficient VLSI Implementation for Fixed-coefficient Multipliers |
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| Xiong Chengyi, Gao Zhirong Tian Jinwen.High Efficient VLSI Implementation for Fixed-coefficient Multipliers[J].Universal Technologies & Products,2003(9):37-38,42. | |
| Authors: | Xiong Chengyi Gao Zhirong Tian Jinwen |
| Affiliation: | Xiong Chengyi1,3 Gao Zhirong2 Tian Jinwen1 |
| Abstract: | Canonic Signal Digital (CSD) is based on the ternary number system (- 1,0,1), which has the advantage of reducing the non- zero bits of the number In this paper, an algorithm for conversion of a 2 's complement to canonic signed digit number system was introduced, and a set of high- efficient multipliers for wavelet filter, based on CSD coding, was presented, in which various optimized techniques for implementation of VLSI was used The design was described by Verilog HDL, which was simulated, synthesized, and mapped into FPGA under Xilinx ISE4 1 The experimental results show that CSD multiplier requires fewer hardware resources and has smaller delay |
| Keywords: | Fixed- coefficient multiplier Canonic Signal Digital VLSI FPGA |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ | |