Stochastic-based placement template generator for analog IC layout-aware synthesis |
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Affiliation: | 1. School of Electrical and Computer Engineering, University of Tehran, Iran;2. Department of Electrical Engineering, University of Southern California, USA;1. Institute of High Performance Computing and Networking, CNR, Naples, Italy;2. Institute of Computer Science, Polish Academy of Sciences, Warsaw, Poland;3. Computer Science Laboratory, University of Science and Technology of Lille, France;4. Polish-Japanese Institute of Information Technology, Warsaw, Poland;1. Institute of High Performance Computing and Networking, CNR, Naples, Italy;2. Institute of Computer Science, Polish Academy of Sciences, Warsaw, Poland;3. University of Lille, CNRS, Centrale Lille, UMR 9189 – CRIStAL, F-59000 Lille, France;4. Polish-Japanese Academy of Information Technology, Warsaw, Poland;1. Electrical and Computer Engineering Department, University of Illinois at Urbana-Champaign, Urbana, IL, United States;2. Intel Corporation, Hillsboro, OR, United States |
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Abstract: | In this paper, a methodology for automatic generation of placement templates for analog integrated circuit design targeted to state-of-the-art optimization-based layout-aware circuit-sizing flows, is proposed. The multi-objective optimization-based placement template generator inputs a Pareto set of sizing solutions and outputs a set of optimal sizing-independent non-slicing B*-tree floorplan representations, i.e., placement templates. Those templates fit the current state of the optimization process and are used within the layout-aware synthesis methodology to generate the floorplan of the following candidate solutions. This innovative methodology combines the advantages of template-based placement approaches, due to its fast packing, with the optimization-based ones, presenting floorplan solutions with improved compactability through the complete evolution of the Pareto set, completely eliminating the template setup effort. Moreover, as the placement template generator runs in parallel with the layout-aware loop, it has no impact on the overall execution time. Experimental results show that the proposed methodology outperforms state-of-the-art multi-template layout-aware synthesis approaches by achieving smaller placement areas for the same performances earlier in the optimization, and further, with a strongly reduced setup effort. |
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Keywords: | Analog integrated circuits In-loop layout generation Layout-aware sizing Electronic design automation Multi-objective optimization Placement template |
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