Exploiting bounds optimization for the semi-formal verification of analog circuits |
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| Affiliation: | 1. Instituto Nacional de Astrofísica Óptica y Electrónica, Puebla, Mexico;2. Instituto Tecnológico de Puebla, Puebla, Mexico;3. New Mexico State University, Las Cruces, NM, USA;4. Spycotec, Fracc. Paseos del Angel Puebla, Puebla. +52-2228870916, Mexico;5. Benemérita Universidad Autónoma de Puebla, Puebla, Mexico;6. Instituto Tecnológico de Cd. Guzmán, Av. Tecnológico #100, Cd. Guzmán, Jal., Mexico;1. Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China;2. Department of Electrical Engineering, Tongji University, Shanghai, China;1. Department of Electrical and Computer Engineering, The University of Tehran, Tehran, Iran;2. School of Computer Science, Institute for Research in Fundamental Sciences, Tehran, Iran;1. Center of Nano Electronics and Devices, American University in Cairo/Zewail City of Science and Technology, Cairo, Egypt;2. Mechatronics Department, Ain-Shams University, Cairo, Egypt;3. Integrated Circuits Lab, Ain-Shams University, Cairo, Egypt |
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| Abstract: | This paper proposes a semi-formal methodology for modeling and verification of analog circuits behavioral properties using multivariate optimization techniques. Analog circuit differential models are automatically extracted and their qualitative behavior is computed for interval-valued parameters, inputs and initial conditions. The method has the advantage of guaranteeing the rough enclosure of any possible dynamical behavior of analog circuits. The circuit behavioral properties are then verified on the generated transient response bounds. Experimental results show that the resulting state variable envelopes can be effectively employed for a sound verification of analog circuit properties, in an acceptable run-time. |
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| Keywords: | Analog circuits Global optimization Verification Qualitative simulation |
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