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Run-time management of systems with partially reconfigurable FPGAs
Affiliation:1. Institute of Computer Science Foundation for Research and Technology (FORTH-ICS), Heraklion, Greece;2. School of Electronic and Computer Engineering Technical University of Crete, Chania, Greece;1. Department of Information Engineering, Electronics and Telecommunications (D.I.E.T.), Sapienza University of Rome, via Eudossiana 18, 00184 Rome, Italy;2. Center for Life Nano Science@Sapienza, Istituto Italiano di Tecnologia, Viale Regina Elena 291, 00161 Rome, Italy;3. Division of Health Protection Technologies, ENEA, via Anguillarese 301, 00123 Rome, Italy;1. Bogazici University, Department of Electrical and Electronics Engineering, Turkey;2. Istanbul Technical University, Department of Electrical and Electronics Engineering, Turkey;1. School of Electrical and Computer Engineering, University of Tehran, Iran;2. Department of Electrical Engineering, University of Southern California, USA;1. Electrical and Computer Engineering Department, University of Illinois at Urbana-Champaign, Urbana, IL, United States;2. Intel Corporation, Hillsboro, OR, United States
Abstract:Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the functionality of computing systems by swapping in and out HW tasks. To coordinate the on-demand task execution, we propose and implement a Run-Time System Manager (RTSM) for scheduling software (SW) tasks on available processor(s) and hardware (HW) tasks on any number of reconfigurable regions (RRs) of a partially reconfigurable FPGA. Fed with the initial partitioning of the application into tasks, the corresponding task graph, and the available task mappings, the RTSM controls system operation considering the status of each task and region (e.g. busy, idle, scheduled for reconfiguration/execution, etc). Our RTSM supports task reuse and configuration prefetching to minimize reconfigurations, task movement among regions to efficiently manage the FPGA area, and region reservation for future reconfiguration and execution. We validate the correctness and portability of our RTSM executing an image processing application on two Xilinx-based platforms: ZedBoard and XUPV5. We also perform a more extensive evaluation of its features using a simulation framework, and find that – despite the technology limitations – our approach can give promising results in terms of scheduling quality. Since our RTSM supports also the scheduling of parallel SW tasks, we use it to manage the execution of the entire parallel Edge Detection application on a desktop; we compare the application execution time with that using the OpenMP framework and find that with our RTSM execution is 2.4 times faster than the unoptimized OpenMP version. When processor affinity optimization is enabled for OpenMP, our RTMS and the OpenMP are on par, indicating that the scheduling efficiency of our RTSM is competitive to this state-of-the-art scheduler, while supporting in addition the management of HW tasks.
Keywords:Run time system  Scheduling  Partial reconfiguration  FPGA  OpenMP
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