A hardened network-on-chip design using runtime hardware Trojan mitigation methods |
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Affiliation: | 1. Department of Electrical and Electronic Engineering (CTC/UFSC) 88040 Florianópolis, Brazil;2. INESC-ID, IST, Universidade de Lisboa, 1000‐029 Lisbon, Portugal;3. Department of Electrical and Electronic Engineering (CTC/UFSC) 88040 Florianópolis, Brazil;4. INESC-ID, IST, Universidade de Lisboa, 1000‐029 Lisbon, Portugal;1. School of Electronic and Information Engineering, Harbin Institute of Technology Shenzhen Graduate School, China;2. Advanced Micro Devices, Inc. (AMD), Shanghai, China;3. SKLCA, Institute of Computing Technology, Chinese Academy of Sciences, China;4. Department of Electrical and Computer Engineering, University of Maryland College Park, USA;1. Dependable System Design Lab., School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran;2. School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran;1. Polytechnique Montreal, Canada;2. CEA-Leti, Grenoble, France;3. Université du Québec à Montréal (UQAM), Canada |
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Abstract: | Due to the globalized semiconductor business model, malicious hardware modifications, known as hardware Trojans (HTs), have risen up as a big concern for chip security. HT detection and mitigation methods for general integrated circuits have been investigated in the past decade. However, the majority of the existing efforts are not customized for HTs in Networks-on-Chip (NoCs). To complement the firmware and software level methods for rogue NoCs detection, we propose countermeasures to harden the NoC hardware design against tampering. More specifically, we propose a collaborative dynamic permutation and flit integrity check method to mitigate the potential inside-router HTs inserted by the disloyal member in the NoC design house or the 3rd-party system integration company. Our method improves the number of received packets by up to 70.1% over the other methods if the HT controls the NoC packet destination address. The average link availability of our method is 43.7% higher than that of the exiting methods. Our method increases the effective average latency by up to 63.4%, 68.2%, and 98.9% for the single HT in the destination, header, and tail fields, respectively, over the existing methods. |
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Keywords: | Hardware Trojan Hardware security Network-on-chip (NoC) Bandwidth depletion Deadlock Livelock Denial-of-service attack Latency Throughput |
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