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IPRM: IP core resource multiplexing of core wrapper design for reducing test application time in DVFS-based multicore SoCs
Affiliation:1. School of Information and Electrical Engineering Harbin Institute of Technology at Weihai, Weihai, Shandong 264209, China;2. Department of Automatic Test and Control Harbin Institute of Technology, Harbin, Heilongjiang 150080, China;1. Department of Information Engineering, Electronics and Telecommunications (D.I.E.T.), Sapienza University of Rome, via Eudossiana 18, 00184 Rome, Italy;2. Center for Life Nano Science@Sapienza, Istituto Italiano di Tecnologia, Viale Regina Elena 291, 00161 Rome, Italy;3. Division of Health Protection Technologies, ENEA, via Anguillarese 301, 00123 Rome, Italy;1. Bogazici University, Department of Electrical and Electronics Engineering, Turkey;2. Istanbul Technical University, Department of Electrical and Electronics Engineering, Turkey;1. School of Electrical and Computer Engineering, University of Tehran, Iran;2. Department of Electrical Engineering, University of Southern California, USA;1. Electrical and Computer Engineering Department, University of Illinois at Urbana-Champaign, Urbana, IL, United States;2. Intel Corporation, Hillsboro, OR, United States
Abstract:A modify wrapper/test access mechanism(TAM) structure is described to explore the maximal potential capacity of TAM, named “IP cores resource multiplexing(IPRM)”, reducing test application time for DVFS-based multicore System-on-Chips(MSoCs). The IPRM core wrappers, different from standard wrappers, enable to isolated core wrapper resource again to store test data for embedded cores under test. An integer linear programming (ILP) formulation with IPRM wrapper is proposed to improve multi-site test. Experimental results of the ITC’02 SoC Benchmark show that IPRM core wrapper reduces the burdens on ATE effectively, and can reduce the test application time by 10–50%.
Keywords:Multicore SoC testing  Wrapper structure design  IP core resource multiplexing  DVFS  Design for testability
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