Configurable memristive logic block for memristive-based FPGA architectures |
| |
| Affiliation: | 1. Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong;2. Department of Micro- and Nano- Electronics, Shanghai Jiao Tong University, Shanghai, China;1. School of Electronic and Information Engineering, Harbin Institute of Technology Shenzhen Graduate School, China;2. Advanced Micro Devices, Inc. (AMD), Shanghai, China;3. SKLCA, Institute of Computing Technology, Chinese Academy of Sciences, China;4. Department of Electrical and Computer Engineering, University of Maryland College Park, USA |
| |
| Abstract: | This article proposes a Configurable Memristive Logic Block (CMLB) that comprises of novel memristive logic cells. The memristive logic cells are constructed from memristive D flip-flop, 6-bit non-volatile look-up table (NVLUT), and multiplexers. The memristive logic cells are interconnected using memristive switch matrix cells to form the CMLB. The CMLB is then used to construct a memristor-based FPGA architecture. The proposed CMLB shows a reduction of 8.6% of device area and 1.094 times lesser critical path delay against the SRAM-based FPGA architecture. Against similar CMOS-based circuits, the memristive D flip-flop provides switching speed of 1.08 times faster, the NVLUT reduces power consumption by 6.25 nW, and the memristive logic cells reduce device area by 60.416 µm2. In this research work also, various memristor-based FPGA architectures found in the literature are compared against the SRAM-based FPGA architecture. |
| |
| Keywords: | FPGA Architecture Memristor Logic block Switch block Configurable logic block |
| 本文献已被 ScienceDirect 等数据库收录！ |
|
