首页 | 本学科首页   官方微博 | 高级检索  
     


A 1.9-GHz Single-Chip CMOS PHS Cellphone
Authors:Si  W W Mehta  S Samavati  H Terrovitis  M Mack  M Onodera  K Jen  S Luschas  S Hwang  J Mendis  S Su  D Wooley  B
Affiliation:Atheros Commun., Santa Clara, CA;
Abstract:A single-chip CMOS PHS cellphone, integrated in a 0.18-mum CMOS technology, implements all handset functions including radio, voice, audio, MODEM, TDMA controller, CPU, and digital interfaces. Both the receiver and transmitter are based on a direct conversion architecture. The RF transceiver achieves -106 dBm receive sensitivity and +4 dBm EVM-compliant transmit power. The local oscillator, based on a sigma-delta fractional-N synthesizer, has a phase noise of -118 dBc/Hz at 600kHz offset and settling time of 15 mus. The current consumption for the receiver, transmitter and synthesizer are 32 mA, 29 mA, and 25 mA, respectively, from a 3.0 V supply
Keywords:
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号