Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memoryarray processor applications

We have fabricated a high yield integrated memory array processor (IMAP) LSI, which features a high memory bandwidth (1.28-GB/s) and low power consumption (4-W max.) and which contains a 2-Mb SRAM with 1.28-I/O's and 64 processor elements (PE's) in one chip. A high-bandwidth and low-power memory circuit design is the key technology to realize the IMAP-LSI. We adopted following new designs for memory circuit. (1) Memory access time is designed to be twice as fast as PE execution time (2) Employment of dynamic power control mode, which reduces the memory power consumption down to 30% of maximum power without a loss in access-speed (3) Simplified synchronization with PE's (4) 4-way block redundancy. These design techniques are suitable for future system integrated ULSI's