A 40-mW 55 Mb/s CMOS equalizer for use in magnetic storage readchannels |
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Authors: | Pai PKD Abidi AA |
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Affiliation: | Dept. of Electr. Eng., California Univ., Los Angeles, CA; |
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Abstract: | A monolithic active equalizer in 2-μm CMOS technology is described, suitable for use in magnetic storage read channels employing peak-detection. Computer simulation of the channel and numerical optimization of equalizer performance have led to a 4-pole equalizer which outperforms conventional 7-pole linear-phase pulse-slimming equalizers. Circuits with matched and scaled stray capacitances use low transconductance amplifiers, with a total on-chip power dissipation of 40 mW (excluding output buffers). A master-slave architecture tunes filter pole frequencies and quality factors (Q) to their nominal values against process and temperature variations |
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