针对Xilinx可编程片上系统的硬件加速方案的研究

当前嵌入式计算应用不断增加,嵌入式系统需要具备相当的处理能力以满足应用需求.在系统中耦合一个专用硬件处理模块来加速某种计算机密集型应用是一种被广泛采纳的有效手段.针对基于Xilinx FPGA的可编程片上系统,从体系结构角度分别研究了三种形式的硬件加速方案:(1)与CPU耦合的协处理器;(2)挂接在PLB总线上的加速器;(3)挂接在MPMC Switch Fabric上的加速器.分析了三种方案各自的特点.在实验环节选取了128位AES加密算法,并在Xilinx Virtex5 器件上做了硬件实现,结果表明基于MPMC扩展的加速器方案性能较好,CPU占用率最低.

Study of Hardware Accelerating Schemes for Xilinx System on Programmable Chip

With the trend of increasing popularity on embedded computing applications,embedded systems need to embrace considerable computing power to meet the requirements of the applications.A widely adopted method to improve the performance is to integrate dedicated hardware processing engines.Targeting the Xilinx System-on-Programmable-Chip,we studied three methods for hardware acceleration:(1)CPU coprocessor;(2)hardware accelerator that placed on PLB bus;(3)hardware accelerator connected with MPMC.We analyzed eac...