| IEEE 1149.7 CJTAG IP核复位与选择单元模块设计 |
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| 引用本文： | 侯杏娜,陈寿宏,马峻,何正亮. IEEE 1149.7 CJTAG IP核复位与选择单元模块设计[J]. 电子测量技术, 2017, 40(11): 52-55. DOI: 10.3969/j.issn.1002-7300.2017.11.012 |
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| 作者姓名： | 侯杏娜 陈寿宏 马峻 何正亮 |
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| 作者单位： | 1.桂林电子科技大学电子工程与自动化学院 桂林 541004； 2.广西自动检测技术与仪器重点实验室 桂林 541004,1.桂林电子科技大学电子工程与自动化学院 桂林 541004； 2.广西自动检测技术与仪器重点实验室 桂林 541004,1.桂林电子科技大学电子工程与自动化学院 桂林 541004； 2.广西自动检测技术与仪器重点实验室 桂林 541004,1.桂林电子科技大学电子工程与自动化学院 桂林 541004； 2.广西自动检测技术与仪器重点实验室 桂林 541004 |
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| 基金项目： | 广西自然科学基金重点项目，广西自然科学基金回国项目，广西自动检测技术与仪器重点实验室基金，广西高等学校优秀中青年骨干教师培养工程资助项目 |
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| 摘 要： | 在深入研究IEEE 1149.7标准基础上,针对测试问题,构建符合标准架构的测试目标芯片CJTAG IP核,重点介绍IP核中复位与选择单元(RSU)模块的设计实现.该模块主要实现了四大功能:确定芯片启动模式、产生复位信号、逃脱检测及选择序列产生、IP核在线或离线选择.基于Quartus Ⅱ应用平台设计,通过ModelSim完成仿真验证.仿真结果表明,该复位与选择单元模块产生的信号符合IEEE1149.7标准规定,能够支持目标芯片IP核实现相应的测试功能.
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| 关 键 词： | IEEE 1149.7； CJTAG； IP核； 复位与选择单元 |
Design of reset and selection unit module in IEEE1149.7 CJTAG IP core |
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| Hou Xingn,Chen Shouhong,Ma Jun and He Zhengliang. Design of reset and selection unit module in IEEE1149.7 CJTAG IP core[J]. Electronic Measurement Technology, 2017, 40(11): 52-55. DOI: 10.3969/j.issn.1002-7300.2017.11.012 |
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| Authors: | Hou Xingn Chen Shouhong Ma Jun He Zhengliang |
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| Affiliation: | School of Electronic Engineering and Automation, Guilin University of Electronic Technology, Guilin 541004, China;Guangxi Key Laboratory of Automatic Detecting Techno1ogy and Instruments, Guilin 541004, China,School of Electronic Engineering and Automation, Guilin University of Electronic Technology, Guilin 541004, China;Guangxi Key Laboratory of Automatic Detecting Techno1ogy and Instruments, Guilin 541004, China,School of Electronic Engineering and Automation, Guilin University of Electronic Technology, Guilin 541004, China;Guangxi Key Laboratory of Automatic Detecting Techno1ogy and Instruments, Guilin 541004, China and School of Electronic Engineering and Automation, Guilin University of Electronic Technology, Guilin 541004, China;Guangxi Key Laboratory of Automatic Detecting Techno1ogy and Instruments, Guilin 541004, China |
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| Abstract: | Based on the in-depth study of IEEE1149.7 standard,the paper designs and implements the target chip CJTAG IP core in the test architecture proposed by standard to solve the problem of test.The design and implementation of reset and selection unit (RSU)module is mainly introduced.The RSU module mainly realizes four functions:Start-up options choice,reset signals generation,escape detection,RSU online/offline choice.The design is based on the Quartus Ⅱ application platform and through the ModelSim to complete the simulation and verification.The simulation results show that the test signals generated by the RSU module can meet the requirements of IEEE1149.7,and can be able to achieve the appropriate test function of the CJTAG chip. |
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| Keywords: | IEEE1149.7 CJTAG IP core reset and selection unit(RSU) |
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