| 一种AES密码算法的硬件实现 |
| |
| 引用本文： | 王赜坤,陈松涛. 一种AES密码算法的硬件实现[J]. 现代电子技术, 2010, 33(16): 10-13 |
| |
| 作者姓名： | 王赜坤 陈松涛 |
| |
| 作者单位： | 1. 武汉理工大学华夏学院,湖北,武汉,430223
2. 烽火通信公司,湖北,武汉,430223 |
| |
| 摘 要： | 介绍了一种适用于较小面积应用场合AES密码算法的实现方案。结合该算法的特点,在常规轮变换中提出一种加/解密列混合变换集成化的硬件结构设计,通过选择使用同一个模块,可以实现加密和解密中的线性变换,既整合了部分加/解密硬件结构,又节约了大量的硬件资源。仿真与综合结果表明,加/解密运算模块面积不超过25000个等效门,有效地减小了硬件实现面积,同时该设计方案也满足实际应用性能的需求。
|
| 关 键 词： | AES算法 复合域算法 轮变换 加/解密硬件结构 |
Hardware Implementation of AES Cipher Algorithm |
| |
| WANG Ze-kun,CHEN Song-tao. Hardware Implementation of AES Cipher Algorithm[J]. Modern Electronic Technique, 2010, 33(16): 10-13 |
| |
| Authors: | WANG Ze-kun CHEN Song-tao |
| |
| Affiliation: | 1.Huaxia College,Wuhan University of Technology,Wuhan 430223,China;2.Fiberhome Co.Ltd.,Wuhan 430223,China) |
| |
| Abstract: | An implementation of AES cipher algorithm for limited area application is introduced.In the normal round transformation,the combination of addroundkey transformation and（Inv）MixColumns transformation is presented for eliminating the difference between encryption and decryption in hardware architecture,and linear transformation is achieved when data is encrypted or decrypted in the certain condition choice.Simulation and synthesis results show that the encryption and decryption operation modules are no more than 25k gates,and can reduce the size of the hardware implementation more effectively.The design can meet the requirements in performance. |
| |
| Keywords: | AES algorithm composite field arithmetic round transformation encryption and decryption hardware architecture |
| 本文献已被 维普 万方数据 等数据库收录！ |
|
