BIT试验中VME总线故障注入设备控制单元设计

针对航空电子设备BIT(机内测试)试验，设计了一种基于FPGA（现场可编程门阵列）的VME总线故障注入设备。该设备的控制单元用于完成故障注入设备的总体控制，是实现故障注入任务的关键。详细分析了VME总线故障注入设备的总体框架，给出了VME总线故障注入设备控制单元的设计方案，包括详细的软、硬件设计方法以及该系统的工作流程，并通过测试工具验证了控制单元设计和功能的正确性。最后，讨论了BIT试验中故障注入技术应用未来研究工作的开展方向。

Design of control module for VME bus fault injection system in BIT experiment

To realize the BIT experiment for avionics, this paper put forward an architecture of VME bus fault injection equipment based on FPGA. The control module, the key for the fault injecting realization, had the function of the overall control for the equipment. Proposed the software and hardware design of control module for the fault injection equipment and the workflow of the fault injection system in detail, based on the framework of VME bus fault injection equipment. This paper also proposed the design pattern for the control module of fault injection equipment, which contained detailed design techniques and system workflow. Moreover, validated the design and function of control module by test tools. At last, it discussed the research prospect of fault injection technique in BIT experiment.