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An Efficient Test Data Compression Technique Based on Codes
作者姓名:Fang Jianping  Hao Yue  Liu Hongxi  Li Kang
作者单位:Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices,School of Microelectronic,Xidian University,Xi’an 710071,China;Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices,School of Microelectronic,Xidian University,Xi’an 710072,China;Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices,School of Microelectronic,Xidian University,Xi’an 710073,China;Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices,School of Microelectronic,Xidian University,Xi’an 710074,China
基金项目:国家科技攻关项目 , 中国科学院资助项目
摘    要:提出了一种新的测试数据压缩/解压缩的算法,称为混合游程编码,它充分考虑了测试数据的压缩率、相应硬件解码电路的开销以及总的测试时间.该算法是基于变长-变长的编码方式,即把不同游程长度的字串映射成不同长度的代码字,可以得到一个很好的压缩率.同时为了进一步提高压缩率,还提出了一种不确定位填充方法和测试向量的排序算法,在编码压缩前对测试数据进行相应的预处理.另外,混合游程编码的研究过程中充分考虑到了硬件解码电路的设计,可以使硬件开销尽可能小,并减少总的测试时间.最后,ISCAS 89 benchmark电路的实验结果证明了所提算法的有效性.

关 键 词:测试数据压缩  不确定位填充  SoC测试  混合游程编码  test  data  compression  unspecified  bits  assignment  system-on-a-chip  test  hybrid  run-length  codes  编码  硬件开销  测试数据  压缩方法  Codes  Based  Technique  Test  Data  Compression  experimental  comparison  decoder  novel  algorithm  vectors  fill  bits  step  new  method  based  improve
文章编号:0253-4177(2005)11-2062-07
收稿时间:2005-04-15
修稿时间:2005-06-10

An Efficient Test Data Compression Technique Based on Codes
Fang Jianping,Hao Yue,Liu Hongxi,Li Kang.An Efficient Test Data Compression Technique Based on Codes[J].Chinese Journal of Semiconductors,2005,26(11):2062-2068.
Authors:Fang Jianping  Hao Yue  Liu Hongxia and Li Kang
Abstract:This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes.The method makes a full analysis of the factors which influence test parameters:compression ratio,test application time,and area overhead.To improve the compression ratio,the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step.With a novel on-chip decoder,low test application time and low area overhead are obtained by hybrid run length codes.Finally,an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method.
Keywords:test data compression  unspecified bits assignment  system-on-a-chip test  hybrid run-length codes
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