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| 对称三进制逻辑CMOS电路的试制 | |
| 引用本文： | 李树荣. 对称三进制逻辑CMOS电路的试制[J]. 微电子学, 1988, 0(4) |
| 作者姓名： | 李树荣 |
| 作者单位： | 天津大学电子工程系 |
| 摘 要： | 根据有关对称三进制逻辑的资料,结合CMOS电路生产工艺特点,设计并试制了对称三值逻辑CMOS系列电路。其中包括倒相器与非门、或非门、变形反相器和T门共五种基本电路。本文叙述了设计方案,生产工艺及结果讨论。 |
| 关 键 词： | 对称三进制逻辑 三值逻辑 CMOS电路 对称性 |
The Development of CMOS Symmetrical Ternary Logic Circuit |
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| Li Shurong. The Development of CMOS Symmetrical Ternary Logic Circuit[J]. Microelectronics, 1988, 0(4) | |
| Authors: | Li Shurong |
| Abstract: | A CMOS symmetrical three-valued ternary logic circuit was designed and fabricated, based on the information associated with symmetrical ternary logic combined with CMOS circuit processing features. It consists of five types of fundamental circuits including inverter, NAND gate, NOR gate, ternary inverter and T-gate. Design scheme, processing and results are discussed. |
| Keywords: | Symmetrical ternary logic Three-valued logic CMOS circuit Symmetry |
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