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A security approach for off-chip memory in embedded microprocessor systems
Authors:Romain Vaslin  Guy Gogniat  Jean-Philippe Diguet  Eduardo Wanderley  Russell Tessier  Wayne Burleson
Affiliation:1. European University of Brittany, CNRS, UMR 3192 – Lab-STICC, Centre de recherche, BP 92116, 56321 Lorient, France;2. CEFET-RN, Natal-RN, CEP 59015-000, Brazil;3. University of Massachusetts, Department of Electrical and Computer Engineering, Amherst, MA 01003, USA;1. University M''Hamed Bougara of Boumerdes, Faculty of Sciences, LIMOSE Laboratory, 5 Avenue de l''indépendance, 35000 Boumerdes, Algeria;2. University of Limoges, 123 rue Albert Thomas, 87000 Limoges, France;1. Dept. of Electricity and Electronics, University of the Basque Country, Vizcaya, Spain;2. Dept. of Electronics and Telecomm., University of the Basque Country, Vizcaya, Spain;3. Dept. of Computing and the Digital Environments, Coventry University, Coventry, UK;1. Computer Science Department, University of Limoges, 123 Avenue Albert Thomas, 87060 Limoges, France;2. ANSSI, SGDSN, 51, boulevard de La Tour-Maubourg, 75700 Paris 07 SP, France;3. INRIA, LHS PEC, 263 Avenue Général Leclerc, 35042 Rennes, France;1. Division of Pediatrics, Departments of Cardiology and Pediatric Cardiology, University of Nebraska Medical Center, Omaha, Nebraska;2. Division of Internal Medicine, Departments of Cardiology and Pediatric Cardiology, University of Nebraska Medical Center, Omaha, Nebraska;3. Ultrasound Division, Siemens Medical Solutions USA Inc, Mountain View, California;4. University of Trieste, Trieste, Italy;1. Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad 9177948944 Iran;2. Electronics Research Lab., Department of Microelectronics, Delft University of Technology, Delft, The Netherlands
Abstract:This paper describes a complete off-chip memory security solution for embedded systems. Our security core is based on a one-time pad (OTP) encryption circuit and a CRC-based integrity checking module. These modules safeguard external memory used by embedded processors against a series of well-known attacks, including replay attacks, spoofing attacks and relocation attacks. Our implementation limits on-chip memory space overhead to less than 33% versus memory used by a standard microprocessor and reduces memory latency achieved by previous approaches by at least half. The performance loss for software execution with our solution is only 10% compared with a non-protected implementation. An FPGA prototype of our security core has been completed to validate our findings.
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