Strain sensitivity of gate leakage in strained-SOI nMOSFETs: A benefit for the performance trade-off and a novel way to extract the strain-induced band offset |
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| Authors: | F Rochette X Garros G Reimbold F Andrieu M Cassé M Mouis G Ghibaudo F Boulanger |
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| Affiliation: | 1. Department of Materials Science and Engineering, Korea University, Seoul 136-713, South Korea;2. Department of Material Science & Engineering, Hanyang University, Seoul 133-791, South Korea;1. Department of Physical Metallurgy and Materials Testing, Montanuniversität Leoben, Franz-Josef-Strasse 18, 8700 Leoben, Austria;2. Thermal Sciences and Materials Branch, Air Force Research Laboratory, Materials and Manufacturing Directorate, Wright-Patterson AFB, OH 45433, USA;1. Laboratory of Biomolecular Modeling, Swiss Federal Institute of Technology (EPFL), 1015 Lausanne, Switzerland;2. Swiss Institute of Bioinformatics, Lausanne, Switzerland;3. Instituto de Biología Molecular y Celular de Rosario (IBR-CONICET, UNR), 2000 Rosario, Argentina |
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| Abstract: | The impact of biaxial stress on gate leakage is investigated on fully-depleted silicon-on-insulator (FD-SOI) nMOS transistors, integrating either a standard gate stack or an advanced high-κ/metal gate stack. It is demonstrated that strained devices exhibit significantly reduced leakage currents (up to ?90% at Eox = 11 MV/cm for σtensile = 2.5 GPa). This specific effect is used to extract the conduction band offset ΔEc induced by strain and is shown to be accurate enough to monitor stress in MOSFETs. This new technique is much less sensitive to gate oxide defects than the method based on the threshold voltage shift ΔVT. This accurate experimental extraction allowed us to pick out realistic values for the deformation potentials in silicon (Ξu = 8.5 eV and Ξd = ?5.2 eV), among the published values. |
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