Effect of interface state trap density on the characteristics of n-type,enhancement-mode,implant-free In0.3Ga0.7As MOSFETs |
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| Authors: | J Ayubi-Moak B Benbakhti K Kalna GW Paterson R Hill M Passlack I Thayne A Asenov |
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| Affiliation: | 1. LESIA, Observatoire de Paris, PSL Research University, CNRS, Sorbonne Universités, UPMC Univ. Paris 06, Univ. Paris Diderot, Sorbonne Paris Cité, 5 place Jules Janssen, 92195 Meudon, France;2. Université Grenoble Alpes, CNRS, Institut de Planétologie et d’Astrophysique de Grenoble (IPAG), UMR 5274, Grenoble F-38041, France;3. Université Grenoble Alpes, ISTerre, F-38041 Grenoble, France;4. IAPS-INAF, Istituto di Astrofisica e Planetologia Spaziali, Area di Ricerca di Tor Vergata,Via del Fosso del Cavaliere, 100, 00133, Rome, Italy;5. Institute for Planetary Research, German Aerospace Center (DLR), Rutherfordstraße 2, 12489 Berlin, Germany;6. Institute of Earth and Environmental Science, University of Potsdam, Potsdam, Germany |
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| Abstract: | The effect of interface state trap density, Dit, on the device characteristics of n-type, enhancement-mode, implant-free (IF) In0.3Ga0.7As MOSFETs 1], 2] has been investigated using a commercial drift-diffusion (DD) device simulation tool. Methodology has been developed to include arbitrary Dit distributions in the input simulation decks to more accurately fit the measured subthreshold characteristics of recently reported 1.0 μm gate length IF In0.3Ga0.7As MOSFETs 3]. The impact of interface states on a scaled 30 nm gate length IF MOSFET is also reported. |
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