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A 23-ns 1-Mb BiCMOS DRAM |
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| Authors: | Kitsukawa G. Yanagisawa K. Kobayashi Y. Kinoshita Y. Ohta T. Udagawa T. Miwa H. Miyazawa H. Kawajiri Y. Ouchi Y. Tsukada H. Matsumoto T. Itoh K. |
| Affiliation: | Hitachi Ltd., Tokyo; |
| Abstract: | A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines the NMOS differential circuit on each pair of data lines with a common highly sensitive bipolar circuit. The resulting chip has been verified to have high-speed characteristics while maintaining a wide operating margin and a relatively small chip size of 62.2 mm2, in spite of a 1.3-μm lithography level |
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